Latches and flip-flops are widely used in all types of electronic devices for counting, sampling, and storage of data. There are a number of different types of flip-flops named after their primary function, such as D-type flip-flops (data), J-K flip flops (J and K inputs), and R-S flip-flops (having R and S latches, standing for “reset: and “set”. D flip-flops are a clocked flip-flop having a one clock pulse delay for its output.
However, the operating conditions of the flip-flops can be violated because hold times and setup times are not always consistent with the specifications (such as provided in the data sheets) of the flip flops used. The violation of the operating conditions of the flip-flops can cause them to go into an unstable (metastable) state that can affect the entire operation of the linked systems. Metastability can occur when both inputs to a latch are set at a logic high (11) and are subsequently set at a logic low (00).
Metastability can cause the latch outputs to oscillate unpredictably in a statistically known manner. Such metastable values are then detected by other circuitry as different logic states. It has been realized by both the present inventor and others in the art that the unpredictability of the oscillations could be useful as a random number generator for a multitude of practical uses.
Current designs of physical (true) random number generators based on flip-flop metastability used fixed delay values between their inputs to violate setup and hold timings, in order to provoke metastability. Eventually, the metastable state resolves to some logic level, which is effectively random, depending on the internal noise of the flip-flops. However, the fixed delay values used by the prior art can cause the random number generator to be susceptible to environmental changes. In addition, fixed delay values at large manufacturing variations can make the circuit not work at all or not work at optimal speed.